Programmable logic devices (PLDs) exist as a well-known type of integrated circuit (IC) that may be programmed by a user to perform specified logic functions. There are different types of programmable logic devices, such as programmable logic arrays (PLAs) and complex programmable logic devices (CPLDs). One type of programmable logic device, known as a field programmable gate array (FPGA), is very popular because of a superior combination of capacity, flexibility, time-to-market, and cost.
An FPGA typically includes an array of configurable logic blocks (CLBs), programmable input/output blocks (IOBs), and like type programmable elements. The CLBs and IOBs are interconnected by a programmable interconnect structure. An FPGA may also include various dedicated logic circuits, such as memories, digital clock managers (DCMs), and input/output (I/O) transceivers. Notably, an FPGA may include one or more embedded processors. The programmable logic of an FPGA (e.g., CLBs, IOBs, and interconnect structure) is typically programmed by loading a stream of configuration data (known as a bitstream) into internal configuration memory cells. The bitstream is typically stored in an external nonvolatile memory, such as an erasable programmable read only memory (EPROM). The states of the configuration memory cells define how the CLBs, IOBs, interconnect structure, and other programmable logic are configured.
In particular, present FPGAs include block random access memory (BRAM) integrated into the programmable fabric. BRAMs may be dual-ported, allowing two write ports and two read ports with access to the same block of memory in any given clock cycle. The size of each BRAM typically targets the mid-range of memories used in most applications. For example, VIRTEX-5 FPGAs commercially available from Xilinx, Inc. of San Jose, Calif. include 36 kilobit (kbit) BRAMs.
Some applications, however, require either smaller memory blocks that the provided BRAMs and/or the flexibility of more than two ports per BRAM. For example, some applications may require the use of multiple first-in-first-out (FIFO) memories. Some or all of these FIFO memories may be designed to have sizes smaller than the size of the BRAMs in a target device. When a design having FIFO memories is implemented for a target FPGA device, the implementation may use a BRAM for each FIFO. Such implementation results in inefficient use of resources in the FPGA.
Accordingly, there exists a need in the art for more efficient use of on-chip block memories in an integrated circuit, such as an FPGA, to implement applications having FIFO memories.